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Tilera Targets Data Bottlenecks With 72-Core Chip

February 19, 2013 | Telepresence Options

Tilera-Gx72.jpg

By Rich Miller Data Center Knowledge

Tilera continues to develop new many-core processors built for the massive data processing needs of "hyper-connected" technology companies. Tilera's newest offering is the GX-72, which boosts the number of cores it can harness to address bottlenecks in networks and applications. The new chip, which is being released today, can be used to power servers or as an accelerator an offload engine for x86-based hardware, an approach that broadens the potential uses for the technology.

The GX-72 is optimized for busting bottlenecks in moving large amounts of data. It builds upon Tilera's architecture, which eliminates the on-chip bus interconnect, a centralized intersection where information flows between processor cores or between cores and the memory and I/O. Instead, Tilera employs an on-chip mesh network to interconnect cores.

The GX-72 is a 64-bit system-on-chip (SoC) equipped with 72 processing cores,  4 DDR memory controllers and a big-time emphasis on I/O. This includes 8 ports for 10 Gb Ethernet, 32 for 1Gb Ethernet, 24 lanes of PCIe 2.0 and Tilera's MICA acceleration engine.

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